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D a ta S h e e t , M a y 2 0 0 0
C504
8-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2000-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2000.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a ta S h e e t , M a y 2 0 0 0
C504
8-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
C504 Revision History: Previous Version: Page 35 - 40 41 57 - 60 several several 2000-05 1996-05
Subjects (major changes since last revision) OTP Memory Operation is added. Table on Version Byte Content is added. AC Characteristics of Programming Mode is added.
VCC is replaced by VDD.
Specification for SAH-C504 is removed
Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
8-Bit Single-Chip Microcontroller C500 Family C504
* Fully compatible to standard 8051 microcontroller * Up to 40 MHz external operating frequency * 16 Kbyte on-chip program memory - C504-2R: ROM version (with optional ROM protection) - C504-2E: programmable OTP version - C504-L: without on-chip program memory * 256 byte on-chip RAM * 256 byte on-chip XRAM * Four 8-bit ports - 2 ports with mixed analog/digital I/O capability * Three 16-bit timers/counters - Timer 2 with up/down counter feature Further features are listed next page.
C504
Oscillator Watchdog
On-Chip Emulation Support Module
10-Bit ADC Timer 2 16-Bit Capture/Compare Unit 10-Bit Compare Unit Watchdog Timer T0
XRAM 256 x 8
RAM 256 x 8
Port 0
I/O
Port 1 C500 Core 8-Bit USART Port 2
8-Bit Digital I/O 4-Bit Analog Inputs
T1
I/O
ROM/OTP 16 k x 8
Port 3
8-Bit Digital I/O 4-Bit Analog Inputs
MCB02589
Figure 1
C504 Functional Units
Data Sheet
1
2000-05
C504
* Capture/compare unit for PWM signal generation and signal capturing - 3-channel, 16-bit capture/compare unit - 1-channel, 10-bit compare unit * Full duplex serial interface (USART) * 10-bit A/D Converter with 8 multiplexed inputs * Twelve interrupt sources with two priority levels * On-chip emulation support logic (Enhanced Hooks Technology TM) * Programmable 15-bit Watchdog Timer * Oscillator Watchdog * Fast Power On Reset * Power Saving Modes - Idle mode - Power-down mode with wake-up capability through INT0 * M-QFP-44 package * Temperature ranges: SAB-C504 TA: 0 to 70 C SAF-C504 TA: - 40 to 85 C SAK-C504 TA: - 40 to 125 C (max. operating frequency: 24 MHz) Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies: * The derivative itself, i.e. its function set * the specified temperature range * the package and the type of delivery For the available ordering codes for the C504, please refer to the "Product Information Microcontrollers" which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Data Sheet
2
2000-05
C504
VDD
VSS
VAREF VAGND
XTAL1 XTAL2 RESET EA ALE PSEN CTRAP COUT3
Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O/ 4-Bit Analog Inputs Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O/ 4-Bit Analog Inputs
C504
MCL02590
Figure 2
Logic Symbol
Data Sheet
3
2000-05
C504
33 32 31 30 29 28 27 26 25 24 23 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V GND P1.0 / AN0 / T2 P1.1 / AN1 / T2EX P1.2 / AN2 / CC0 P1.3 / AN3 / COUT0 P1.4 / CC1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V DD V SS XTAL1 XTAL2 P3.7 / RD P3.6 / WR / INT2
P1.5 / COUT1 P1.6 / CC2 P1.7 / COUT2 RESET P3.0 / RxD CTRAP P3.1 / TxD P3.2 / AN4 / INT0 P3.3 / AN5 / INT1 P3.4 / AN6 / T0 P3.5 / AN7 / T1
P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA COUT3 ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13
C504-LM C504-2RM C504-2EM 1 2 3 4 5 6 7 8 9 10 11
MCP02532
Figure 3
Pin Configuration (top view)
Data Sheet
4
2000-05
C504
Table 1 Symbol
Pin Definitions and Functions Pin Number I/O1) Function (P-MQFP-44) I/O Port 1 is an 8-bit bidirectional port. Port 1 pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D converter. As secondary digital functions, Port 1 contains the Timer 2 pins and the Capture/Compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of Port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 / input to Timer 2 P1.1 / AN1 / T2EX Analog input channel 1 / capture/reload trigger of Timer 2 up-down count P1.2 / AN2 / CC0 Analog input channel 2 / input/output of capture/ compare channel 0 P1.3 / AN3 / COUT0 Analog input channel 3 / output of capture/compare channel 0 P1.4 / CC1 Input/output of capture/ compare channel 1 P1.5 / COUT1 Output of capture/compare channel 1 P1.6 / CC2 Input/output of capture/ compare channel 2 P1.7 / COUT2 Output of capture/compare channel 2 I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD.
P1.0 - P1.7 40 - 44, 1-3
40 41
42
43
44 1 2 3 RESET 4
Data Sheet
5
2000-05
C504
Table 1 Symbol
Pin Definitions and Functions (cont'd) Pin Number I/O1) Function (P-MQFP-44) I/O Port 3 is an 8-bit bidirectional port. P3.0 (RxD) and P3.1 (TxD) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, and four of the analog inputs of the A/D converter. Port 3 pins are assigned to be used as analog inputs via the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / AN4 / INT0 Analog input channel 4 / external interrupt 0 input / Timer 0 gate control input P3.3 / AN5 / INT1 Analog input channel 5 / external interrupt 1 input / Timer 1 gate control input P3.4 / AN6 / T0 Analog input channel 6 / Timer 0 counter input P3.5 / AN7 / T1 Analog input channel 7 / Timer 1 counter input P3.6 / WR / INT2 WR control output; latches the data byte from port 0 into the external data memory / external interrupt 2 input RD control output; enables the P3.7 / RD external data memory
P3.0 - P3.7 5, 7 - 13
5
7
8
9
10 11 12
13
Data Sheet
6
2000-05
C504
Table 1 Symbol CTRAP
Pin Definitions and Functions (cont'd) Pin Number I/O1) Function (P-MQFP-44) 6 I CCU Trap Input With CTRAP = low, the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode. XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have "1"s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing "1"s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 special function register.
7 2000-05
XTAL2 XTAL1
14 15
- -
P2.0 - P2.7 18-25
I/O
Data Sheet
C504
Table 1 Symbol PSEN
Pin Definitions and Functions (cont'd) Pin Number I/O1) Function (P-MQFP-44) 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. When instructions are executed from internal ROM (EA = 1) the ALE generation can be disabled by clearing bit EALE in SFR SYSCON. 10-Bit compare channel output This pin is used for the output signal of the 10-bit Compare Timer 2 unit. COUT3 can be disabled and set to a high or low state. External Access Enable When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H. When held at low level, the C504 fetches all instructions from external program memory. For the C504-L, this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have "1"s written to them float; and in that state, can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pullup resistors when issuing "1" s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification. Reference voltage for the A/D converter.
ALE
27
O
COUT3
28
O
EA
29
I
P0.0 - P0.7 37 - 30
I/O
VAREF
Data Sheet
38
-
8
2000-05
C504
Table 1 Symbol
Pin Definitions and Functions (cont'd) Pin Number I/O1) Function (P-MQFP-44) 39 16 17 - - - Reference ground for the A/D converter. Ground (0 V) Power Supply (+ 5 V)
VAGND VSS VDD
1) I = Input, O = Output
Data Sheet
9
2000-05
C504
VDD VSS
XTAL1 XTAL2
Oscillator Watchdog XRAM 256 x 8 OSC & Timing RAM 256 x 8 ROM/OTP 16 k x 8
CPU
RESET ALE PSEN EA
Timer 0
Port 0
Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O 4-Bit Analog Inputs Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O 4-Bit Analog Inputs
Timer 1
Port 1
Timer 2
Port 2
Interrupt Unit
Port 3
USART
COUT3 CTRAP
Capture/Compare Unit
VAREF VAGND
A/D Converter 10-Bit Emulation Support Logic
MCB02591
S&H
MUX
Figure 4
Block Diagram of the C504
Data Sheet
10
2000-05
C504
CPU The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 s (24 MHz: 500 ns, 40 MHz: 300 ns). Special Function Register PSW (Address D0H)
Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1
Reset Value: 00H
LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instructions. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag 0 Register Bank Select Control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag 1 Parity Flag Set/cleared by hardware after each instruction to indicate an odd/ even number of "one" bits in the accumulator.
Data Sheet
11
2000-05
C504
Memory Organization The C504 CPU manipulates operands in the following four address spaces: - up to 64 Kbyte of program memory: 16K ROM for C504-2R 16K OTP for C504-2E - up to 64 Kbyte of external data memory - 256 bytes of internal data memory - 256 bytes of internal XRAM data memory - a 128 byte special function register area Figure 5 illustrates the memory address spaces of the C504.
FFFF H Internal XRAM FEFF H External
FFFF H
FF00 H
Indirect Address FF H External 4000 H 3FFFH Internal (EA = 1) External (EA = 0) 0000 H "Code Space" "Data Space" 0000 H Internal RAM Internal RAM 80 H
Direct Address FF H Special Function Register 80 H 7F H
00 H "Internal Data Space"
MCD02592
Figure 5
C504 Memory Map
Data Sheet
12
2000-05
C504
Reset and System Clock Operation The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This, in turn, may cause unpredictable output operations at several port pins). At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation is the oscillator start-up time and the time for 2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This requirement is typically met using a capacitor of 4.7 to 10 F. The same considerations apply if the reset signal is generated externally (Figure 6b). In each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Figure 6 shows the possible reset circuitries.
a) b)
& RESET + C504 c) C504 + RESET C504
MCS03352
RESET
Figure 6
Data Sheet
Reset Circuitries
13 2000-05
C504
Figure 7 shows the recommended oscillator circuit for the C504, while Figure 8 shows the circuit for using an external clock source.
C XTAL2 3.5 - 40 MHz C XTAL1 C = 20 pF 10 pF for crystal operation
MCS03353
C504
Figure 7
Recommended Oscillator Circuit
V DD
N.C.
C504 XTAL2
External Clock Signal
XTAL1
MCS03355
Figure 8
External Clock Source
Data Sheet
14
2000-05
C504
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3 Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, Port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
Data Sheet
15
2000-05
C504
Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F0H, F8H) are bit-addressable. The SFRs of the C504 are listed in Table 2 and Table 3. In Table 2, they are organized in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.
Data Sheet
16
2000-05
C504
Table 2 Block
Special Function Registers - Functional Blocks Symbol Name Addr. Contents after Reset
00H 00H 00H 00H 00H 07H XX10XXX0B3) 0X000000B3) XX000000B3) 00H XX000000B3) XX000000B3) 00101010B FFH FFH XXXX1111B3) FFH FFH XX1111XXB3) XX000000B3) 01XXX000B3) 00H 00XXXXXXB3) XXXX1111B3) XX1111XXB3) 000X0000B XXH3) 00H 00H 00H 00H 00H 00H 00H
CPU
ACC B DPH DPL PSW SP
Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer SYSCON System Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 3 Analog Input Selection Register
E0H1) F0H1) 83H 82H D0H1) 81H B1H A8H1) A9H D6H B8H1) B9H 9AH 80H1) 90H1) 90H1) 4) A0H1) B0H1) B0H1) 4) D8H1) DCH D9H DAH 90H1) 4) B0H1) 4) 87H 99H 98H1) 88H1) 8CH 8DH 8AH 8BH 89H
Interrupt System
IEN0 IEN1 CCIE2) IP0 IP1 ITCON P0 P1 P1ANA2) P2 P3 P3ANA2)
ADCON0 ADCON1
Ports
A/DConverter
A/D Converter Control Register 0 A/D Converter Control Register 1 ADDATH A/D Converter Data Register High Byte ADDATL A/D Converter Data Register Low Byte P1ANA2) Port 1 Analog Input Selection Register P3ANA2) Port 3 Analog Input Selection Register PCON2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register
Serial Channels Timer 0/ Timer 1
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
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2000-05
C504
Table 2 Block
Special Function Registers - Functional Blocks (cont'd) Symbol Name Addr. Contents after Reset
00H XXXXXXX0B3) 00H 00H 00H 00H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00B3) 00H XXXXXX00B3) 00H XXXX0000B3) 00H 000X0000B3) 0XXXXXXXB3)
Timer 2
T2CON T2MOD RC2H RC2L TH2 TL2 CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE2) CT2CON CP2L CP2H CMP2L CMP2H BCON
Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register
C8H1) C9H CBH CAH CDH CCH E1H DEH DFH E6H E7H E3H E4H E2H CFH C2H C3H C4H C5H C6H C7H E5H D6H C1H D2H D3H D4H D5H D7H C0H1) 86H 87H 88H1) 4)
Capture / Compare Unit
Watchdog Timer Power Saving Mode
WDCON Watchdog Timer Control Register WDTREL Watchdog Timer Reload Register PCON2) PCON1 Power Control Register Power Control Register 1
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
18
2000-05
C504
Table 3 Addr
Contents of the SFRs, SFRs in Numeric Order of their Addresses Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) P0 SP DPL DPH FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL
80H2) 81H 82H 83H 86H 87H 88H2)
.6 .6 .6 .6 .6
.5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 .5 - SM2 .5 I2ETF .5 ET2 ECT1
.4 .4 .4 .4 .4 - TR0 - M0 .4 .4 .4 .4 .4 - REN .4 I2ETR .4 ES
.3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 .3 EAN3 TB8 .3 I1ETF .3 ET1
.2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 .2 EAN2 RB8 .2 I1ETR .2 EX1 ECEM
.1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 T2EX EAN1 TI .1 I0ETF .1 ET0 EX2
.0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 T2 EAN0 RI .0 I0ETR .0 EX0 EADC
WDTREL 00H PCON TCON 000X0000B 00H 0XXXXXXXB 00H 00H 00H 00H 00H FFH XXXX1111B 00H XXH 00101010B FFH 0X000000B XX000000B
SMOD PDS TF1 TR1
88H1)3) PCON1 89H 8AH 8BH 8CH 8DH 90H
2)
EWPD - GATE .7 .7 .7 .7 .7 - SM0 .7 IT2 .7 EA - C/T .6 .6 .6 .6 .6 - SM1 .6 IE2 .6 - -
TMOD TL0 TL1 TH0 TH1 P1
90H2)3) P1ANA 98H2) 99H 9AH A0H2) A8H A9H
2)
SCON SBUF ITCON P2 IEN0 IEN1
ECCM ECT2
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
19
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C504
Table 3 Addr
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) P3 FFH XX1111XXB RD - - - - - CT2P .7 .7 .7 .7 .7 .7 TF2 - .7 .7 .7 .7
B0H2)
WR - - - - -
T1 EAN7 EALE PT2 PCT1 -
T0 EAN6 RMAP PS
INT1 EAN5 - PT1
INT0 EAN4 - PX1 PCEM
TxD - - PT0 PX2
RxD - XMAP PX0 PADC SWDT CLK0 .0 .0 .0 .0 .0 .0 CP/ RL2 DCEN .0 .0 .0 .0
B0H2)3) P3ANA B1H B8H2) B9H
SYSCON XX10XXX0B IP0 IP1 XX000000B XX000000B
PCCM PCT2 - CT2 RES .4 .4 .4 .4 .4 .4 TCLK - .4 .4 .4 .4
C0H2) WDCON XXXX0000B C1H C2H C3H C4H C5H C6H C7H CT2CON 00010000B CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 00H 00H 00H 00H 00H
OWDS WDTS WDT CT2R .3 .3 .3 .3 .3 .3 CLK2 .2 .2 .2 .2 .2 .2 CLK1 .1 .1 .1 .1 .1 .1 C/T2 - .1 .1 .1 .1
ECT2O STE2 .6 .6 .6 .6 .6 .6 EXF2 - .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 RCLK - .5 .5 .5 .5
C8H2) T2CON C9H CAH CBH CCH CDH CFH T2MOD RC2L RC2H TL2 TH2 TRCON
EXEN2 TR2 - .3 .3 .3 .3 - .2 .2 .2 .2
TRPEN TRF
TREN5 TREN4 TREN3 TREN2 TREN1 TREN0
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
20
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C504
Table 3 Addr
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Content Bit 7 after Reset1) 00H 00H XXXX. XX00B 00H XXXX. XX00B 00H 00H CY .7 - .7 - ECTP CP2L CP2H CMP2L CMP2H CCIE BCON
D0H2) PSW D2H D3H D4H D5H D6H D7H
AC .6 - .6 - ECTC
F0 .5 - .5 - CC2 FEN
RS1 .4 - .4 - CC2 REN
RS0 .3 - .3 - CC1 FEN
OV .2 - .2 - CC1 REN
F1 .1 .1 .1 .1 CC0 FEN BCM1 MX1 .3 - MX1 .1 .1 .1 CLK1 COUT 0I
P .0 .0 .0 .0 CC0 REN BCM0 MX0 .2 - MX0 .0 .0 .0 CLK0 CC0I
BCMP PWM1 PWM0 EBCE BCEM - .9 .1 - .8 .0 IADC .7 - BSY .6 - - .4 .4 .4 CT1 RES CC2I
BCERR BCEN ADM .5 - - .3 .3 .3 CT1R COUT 1I MX2 .4 - MX2 .2 .2 .2 CLK2 CC1I
D8H2) ADCON0 XX000000B D9H DAH DCH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H F0H2)
2)
ADDATH 00H ADDATL 00XXXXXXB ADCON1 01XXX000B CCPL CCPH ACC 00H 00H 00H
ADCL1 ADCL0 - .7 .7 .7 CTM COUT 3I .6 .6 .6 ETRP .5 .5 .5 STE1
CT1CON 00010000B COINI FFH
COUTX COUT I 2I
CMSEL0 00H CMSEL1 00H CCIR 00H
CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 0 0 0 0 CC2R .4 .4 .4 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 CC1F .3 .3 .3 CC1R .2 .2 .2 CC0F .1 .1 .1 CC0R .0 .0 .0
CT1FP CT1FC CC2F .7 .7 .7 .6 .6 .6 .5 .5 .5
CT1OFL 00H CT1OFH 00H B 00H
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers
Data Sheet
21
2000-05
C504
Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4. Table 4 Timer/Counter 0 and 1 Operating Modes TMOD Input Clock external (max.) Gate C/T M1 M0 internal 0 1 2 3 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit auto-reload X X X X X X X 0 1 0 1 0 1 0 1
Mode Description
fOSC/12 x 32 fOSC/24 x 32 fOSC/12 fOSC/12 fOSC/12 fOSC/24 fOSC/24 fOSC/24
Timer/counter 0 used as one X 8-bit timer/counter and one 8-bit timer Timer 1 stops
In the "timer" function (C/T = `0'), the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic.
f OSC
/ 12 C/T TMOD 0 P3.4/T0 P3.5/T1 max f OSC/24 TR 0/1 TCON Gate TMOD P3.2/INT0 P3.3/INT1 =1
_ <1
MCS01768
f OSC/12
Timer 0/1 Input Clock 1 Control &
Figure 10
Data Sheet
Timer/Counter 0 and 1 Input Clock Logic
22 2000-05
C504
Timer/Counter 2 Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as a timer or as an event counter. This is selected by bit C/T2 of SFR T2CON. It has three operating modes as shown in Table 5. Table 5
Mode
Timer/Counter 2 Operating Modes
T2CON RxCLK or TxCLK CP/ TR2 RL2 0 0 0 0 1 1 1 1 1 1 T2MOD T2CON P1.1/ T2EX Remarks Input Clock internal external (P1.0/T2) reload upon fOSC/12 overflow reload trigger (falling edge) Down counting Up counting 16 bit Timer/ Counter (only up-counting) capture TH2, TL2 RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") Timer 2 stops fOSC/12 max fOSC/24
DCEN 0 0 1 1 X
EXEN 0 1 X X 0 X 0 1 X
16-bit Autoreload
0 0 0 0
16-bit Capture
0
max fOSC/24
0
1
1
X
1
Baud Rate Generator
1
X
1
X
0
X
fOSC/2
max fOSC/24
1
X
1
X
1
off
X
X
0
X
X
X
-
-
Note: =
falling edge
Data Sheet
23
2000-05
C504
Capture/Compare Unit The Capture/Compare Unit (CCU) of the C504 consists of a 16-bit 3-channel capture/ compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. In capture mode, the value of the Compare Timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx. Figure 11 shows the block diagram of the CCU.
Figure 11
Block Diagram of the CCU
Data Sheet
24
2000-05
C504
The Compare Timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers; each of which has a count rate with a maximum of fOSC/2 up to fOSC/256. The compare timer operations with its possible compare output signal waveforms are shown in Figure 12.
Compare Timer 1 in Operating Mode 0 a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned) with programmable dead time ( t OFF )
Period Value Compare Value 0000 H
Period Value Compare Value Offset
t OFF
CC COUT
CC COUT Compare Timer 1 in Operating Mode 1 c) Symetrical PWM (Center Aligned)
d) Symetrical PWM (Center Aligned) with programmable dead time ( t OFF )
Period Value Compare Value 0000 H CC COINI=0 COUT COINI=1 : Interrupts can be generated
Period Value Compare Value Offset
t OFF t OFF
CC COINI=0 COUT COINI=1
MCT03356
Figure 12
Basic Operating Modes of the CAPCOM Unit
Compare Timer 1 can be programmed for both operating modes while Compare Timer 2 works only in operating mode 0 with one output signal of selectable polarity at the pin COUT3.
Data Sheet 25 2000-05
C504
Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 6. Table 6 Mode 0 0 SM0 USART Operating Modes SCON SM1 0 Baud Rate Description Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first)
fOSC/12
1
0
1
Timer 1/2 overflow rate 8-bit UART 10 bits are transmitted (through TxD) or received (RxD)
2
1
0
fOSC/32 or fOSC/64
9-bit UART 11 bits are transmitted (TxD) or received (RxD)
3
1
1
Timer 1/2 overflow rate 9-bit UART Like mode 2 except the variable baud rate
Timer 2 Overflow Timer 1 Overflow PCON.7 (SMOD) 2 0 T2CON
(RCLK, TCLK)
SM0 / SM1 Mode 1, 3
Phase 2 CLK (= f OSC /2)
0
Baud Rate Clock
Mode 2
1
1
MCB02414
Figure 13
Baud Rate Generation for the Serial Interface
Data Sheet
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2000-05
C504
The possible baud rates can be calculated using the formulas given in Table 7. Table 7 Source of Baud Rate Oscillator Timer 1 (16-bit timer) (8-bit timer with 8-bit auto-reload) Timer 2 Formulas for Calculating Baud Rates Operating Mode 0 2 1, 3 1, 3 1, 3 Baud Rate
(2SMOD x fOSC)/64 (2SMOD x timer 1 overflow rate)/32 (2SMOD x fOSC)/(32 x 12 x (256-TH1))
fOSC/12
fOSC/(32 x (65536-(RC2H, RC2L))
Data Sheet
27
2000-05
C504
10-Bit A/D Converter The C504 has a high performance 8-channel 10-bit A/D converter using successive approximation technique for the conversion of analog input voltages. Figure 14 shows the block diagram of the A/D Converter.
Internal Bus ECT1 ECCM ECT2 ECEM EX2 EADC
IEN1 (A9H ) -
P1ANA (90 H) EAN3 EAN2 EAN1 EAN0
P3ANA (B0 H) EAN7 EAN6 EAN5 EAN4 -
ADCON1 (DCH ) ADCL1 ADCL0 MX2 MX1 MX0
ADCON0 (D8 H) IADC BSY ADM MX2 MX1 MX0
Port 1/3 Clock Prescaler / 32, 16, 8, 4
MUX
S&H
f OSC /2
Conversion Clock f ADC Input Clock f IN
ADDATH ADDATL (D9H ) (DA H) Single/ .2 Continuous .3 Mode .4 .5 .6 .7 A/D Converter .8 LSB MSB .1
VAREF VAGND
Start of Conversion Shaded bit locations are not used in ADC-functions. Write to ADDATL Internal Bus
MCB02616
Figure 14
Data Sheet
A/D Converter Block Diagram
28 2000-05
C504
The A/D Converter uses two clock signals for operation: the conversion clock fADC (= 1/ tADC) and the input clock fIN (= 1/tIN). Both clock signals are derived from the C504 system clock fOSC which is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the fIN clock signal. The table in Figure 15 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates.
MCU System Clock Rate (fOSC)
fIN
[MHz]
Prescaler Ratio /4 /4 /4 /8 /8 / 16 ADCL1 ADCL0 0 0 0 0 0 1 0 0 0 1 1 0
fADC
[MHz]
A/D Conversion Time [s] 48 x tIN = 27.4 48 x tIN = 8 48 x tIN = 6 96 x tIN = 8 96 x tIN = 6 192 x tIN = 9.6
3.5 MHz 12 MHz 16 MHz 24 MHz 32 MHz 40 MHz Figure 15
1.75 6 8 12 16 20
.438 1.5 2 1.5 2 1.25
A/D Converter Clock Selection
The analog inputs are located at Port 1 and Port 3 (4 lines on each port). The corresponding Port 1 and Port 3 pins have a port structure, which allows the pins to be used either as digital I/Os or analog inputs. The analog input function of these mixed digital/analog port lines is selected via the registers P1ANA and P3ANA.
Data Sheet
29
2000-05
C504
Interrupt System The C504 provides 12 interrupt sources with two priority levels. Figures 16 and 17 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.
Figure 16
Data Sheet
Interrupt Request Sources (Part 1)
30 2000-05
C504
P3.6/WR/INT2 IT2 ITCON.7 ITCON.4
_ <1
Low Priority IE2 ITCON.6 EX2 IEN1.1 004B H High Priority PX2 IP1.1
ITCON.5 CC0R P1.2/AN2/CC0 CCIR.0 CC0F CC0REN CCIE0.0 CC0FEN CCIE0.1 CC1REN CCIE0.2 CC1FEN CCIE0.3 CC2REN CCIE0.4 CC2FEN CCIE0.5 ECCM IEN1.4
_ <1
Capture/Compare Match Interrupt
CCIR.1 CC1R P1.4/CC1 CCIR.2 CC1F CCIR.3 CC2R P1.6/CC2 CCIR.4 CC2F CCIR.5 CT1FP Compare Timer 1 Interrupt CCIR.7
0063 H
PCCM IP1.4
ECTP CCIE.7
_ <1
CT1FC CCIR.6 Compare Timer 2 Interrupt TRF CCU Emergency Interrupt Bit addressable Request Flag is cleared by hardware TRCON.6 ETRP CT1CON.6
_ <1
ECT1 IEN1.5 ECTC CCIE.6
006B H
PCT1 IP1.5
CT2P CT2CON.7 ECT2 IEN1.3
005B H
PCT2 IP1.3
BCERR BCON.3 EBCE BCON.4
ECEM IEN1.2
0053 H EA IEN0.7
PCEM IP1.2
MCB02596
Figure 17
Interrupt Request Sources (Part 2)
Data Sheet
31
2000-05
C504
Table 8
Interrupt Vector Addresses Interrupt Source External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt A/D converter interrupt External interrupt 2 CAPCOM emergency interrupt Compare timer 2 interrupt Capture/compare match interrupt Compare timer 1 interrupt Power-down interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 007BH
Request Flags IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 IADC IE2 TRF, BCERR CT2P CC0F-CC2F, CC0R-CC2R CT1FP, CT1FC -
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt sources. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9. Table 9 Interrupt Source Structure Priority Low Priority A/D Converter External Interrupt 2 CCU Emergency Interrupt Compare Timer 2 Interrupt Capture/Compare Match Interrupt Compare Timer 1 Interrupt High
Interrupt Source High Priority External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt
Low
Data Sheet
32
2000-05
C504
Fail Save Mechanisms The C504 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure. - a programmable 15-bit Watchdog Timer - Oscillator Watchdog Programmable Watchdog Timer The Watchdog Timer in the C504 is a 15-bit timer, which is incremented by a count rate of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). Only the upper 7 bits of the 15-bit watchdog timer count value can be programmed. Figure 18 shows the block diagram of the programmable Watchdog Timer.
Figure 18
Block Diagram of the Programmable Watchdog Timer
The Watchdog Timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to refresh the running Watchdog Timer, an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in SFR WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT and SWDT (both in SFR WDCON) consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the Watchdog Timer is halted during the idle mode and power down mode of the processor.
Data Sheet
33
2000-05
C504
Oscillator Watchdog The Oscillator Watchdog of the C504 serves for three functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504 is brought into reset. If the failure condition disappears, the C504 executes a final reset phase of typically 1 ms in order to allow the oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The Oscillator Watchdog unit also works identically to the monitoring function. - Control of external wake-up from software power-down mode When the software power-down mode is terminated by a low level at pin P3.2/INT0, the Oscillator Watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typically 1 ms in order to allow the on-chip oscillator to stabilize.
Data Sheet
34
2000-05
C504
Figure 19
Block Diagram of the Oscillator Watchdog
Power Saving Modes The C504 provides two power saving modes, the idle mode and the power down mode. - In the idle mode, the oscillator of the C504 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D Converter, and all timers with the exception of the Watchdog Timer, are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. - In the power down mode, the RC oscillator and the on-chip oscillator which operates with the XTAL pins are both stopped. Therefore all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFRs are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFRs. Table 10 gives a general overview of the entry and exit procedures of the power saving modes.
Data Sheet
35
2000-05
C504
Table 10 Mode
Power Saving Modes Overview Entering (2-Instruction Example) ORL PCON, #01H ORL PCON, #20H Leaving by Remarks
Idle mode
Occurrence of any enabled interrupt Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock.
Power With external wake-up Hardware Reset Oscillator is stopped; Down mode capability from power P3.2/INT0 goes low Contents of on-chip RAM down enabled and SFRs are maintained. for at least 10 s. ORL SYSCON,#10H It is desired that the ORL PCON1,#80H pin be held at high ANL SYSCON,#0EFH level during the power down mode ORL PCON,#02H entry and up to the ORL PCON,#40H wake-up. With external wake-up Hardware Reset capability from power down disabled ORL PCON,#02H ORL PCON,#40H If a power saving mode is terminated through an interrupt, including the external wakeup via P3.2/INT0, the microcontroller state (CPU, ports, peripherals) remains preserved. If it is terminated by a hardware reset, the microcontroller is reset to its default state. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated.
Data Sheet
36
2000-05
C504
OTP Memory Operation (C504-2E only) The C504-2E is the OTP version of the C504 microcontroller with a 16Kbyte one-time programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 s) with the C504-2E. Several levels of OTP memory protection can be selected as well. To program the device, the C504-2E must be put into the programming mode. Typically, this is not done in-system, but in a special programming hardware. In the programming mode, the C504-2E operates as a slave device similar to an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 20 shows the pins of the C504-2E which are required for controlling of the OTP programming mode.
V DD
V SS
P2.0 - 7 PALE PMSEL0 PMSEL1
Port 2
Port 0
P0.0 - 7
EA / V PP PROG
C504-2E
PRD
RESET XTAL1 XTAL2 PSEN PSEL
MCS03360
Figure 20
C504-2E Programming Mode Configuration
Data Sheet
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2000-05
C504
Pin Configuration in Programming Mode
33 32 31 30 29 28 27 26 25 24 23 D3 D2 D1 D0 N.C. N.C. N.C. N.C. N.C. N.C. N.C. 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 V DD V SS XTAL1 XTAL2 N.C. N.C.
N.C. N.C. N.C. RESET PMSEL0 N.C. PMSEL1 PSEL PRD PALE N.C.
D4 D5 D6 D7 EA / V PP N.C. PROG PSEN A7 A6 A5 / A13
C504-2E 1 2 3 4 5 6 7 8 9 10 11
MCP03361
Figure 21
Pin Configuration of the C504-2E in Programming Mode (top view)
Data Sheet
38
2000-05
C504
Pin Definitions Table 11 contains the functional description of all C504-2E pins which are required for OTP memory programming. Table 11 Symbol RESET Pin Definitions and Functions of the C504-2E in Programming Mode Pin No. P-MQFP-44 4 I Reset This input must be at static "1" (active) level throughout the entire programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PMSEL0 0 1 0 1 Access Mode Reserved Read version bytes Program/read lock bits Program/read OTP memory byte I/O Function
PMSEL0 5 PMSEL1 7
I I
PSEL
8
I
Basic programming mode select This input is used for the basic programming mode selection and must be switched according to Figure 22. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier.
39 2000-05
PRD
9
I
PALE
10
I
XTAL2
14
O
Data Sheet
C504
Table 11 Symbol XTAL1
Pin Definitions and Functions of the C504-2E in Programming Mode (cont'd) Pin No. P-MQFP-44 15 16 17 18 - 25 I - - I XTAL1 Input to the oscillator amplifier. Ground (0 V) must be applied in programming mode. Power Supply (+ 5 V) must be applied in programming mode. Address lines P2.0 - P2.7 are used as multiplexed address input lines A0 - A7 and A8 - A13. A8 - A13 must be latched with PALE. Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection, a low level must be applied to PROG. Programming Voltage This pin must be held at 11.5 V (VPP) during programming of an OTP memory byte or lock bit. During an OTP memory read operation, this pin must be at VIH. This pin is also used for basic programming mode selection. For basic programming mode selection, a low level must be applied. Data lines In programming mode, data bytes are transferred via the bidirectional D7 - D0 data lines which are located at Port 0. Not Connected These pins should not be connected in programming mode. I/O Function
VSS VDD
P2.0 P2.7
PSEN
26
I
PROG
27
I
EA/VPP
29
-
P0.7 P0.0
30-37
I/O
N.C.
1-3, 6, 11-13, 28, 38-44
-
Data Sheet
40
2000-05
C504
Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: - Basic programming mode selection - Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/ read, version byte read, and program/read lock byte operations. The basic programming mode selection scheme is shown in Figure 22.
5V
VDD
Clock (XTAL1/ XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1"
"0"
VPP
EA/VPP 0V
VIH
Ready for access mode selection
MCT03362
During this period signals are not actively driven
Figure 22
Basic Programming Mode Selection
Data Sheet
41
2000-05
C504
Table 12
Access Modes Selection EA/ PROG PRD PMSEL 1 H H H H L - D1,D0 see Table 13 H 0 H
Access Mode Program OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte
VPP VPP
Address (Port 2) A0 - A7 A8 - A15
Data (Port 0) D0 - D7
Read OTP memory byte VIH
VPP VIH H VIH
H
L
H
Byte addr. D0 - D7 of version byte
Lock Bits Programming / Read The C504-2E has two programmable lock bits which, when programmed according to Table 13, provide four levels of protection for the on-chip OTP code memory. Table 13 Lock Bits D1 1 1 D0 1 0 Lock Bit Protection Types Protection Protection Type Level Level 0 Level 1 The OTP lock feature is disabled. During normal operation of the C504-2E, the state of the EA pin is not latched on reset. During normal operation of the C504-2E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to ROM/OTP verification mode 2. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using ROM verification mode 2 is disabled. Same as level 2; but additionally external code execution by setting EA = low during normal operation of the C504-2E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.
0 0
1 0
Level 2 Level 3
Note: A `1' means that the lock bit is unprogrammed; a `0' means that lock bit is programmed.
Data Sheet 42 2000-05
C504
Version Bytes The C504-2E and C504-2R provide three version bytes at mapped address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step. Therefore, the version bytes can be read but not written. The three version bytes hold information as manufacturer code, device type, and stepping code. The steppings of the C504 contain the following version byte information: Table 14 Stepping Content of Version Bytes Version Byte 1, Version Byte 2, Version Byte 0, VR0 (mapped addr. VR1 (mapped addr. VR2 (mapped addr. FDH) FEH) FCH) C5H C5H C5H C5H 04H 84H 84H 84H 01H 01H 04H 09H
C504-2R AC-Step C504-2E ES-AA-Step C504-2E ES-BB-Step C504-2E CA-Step
Future steppings of the C504 will typically have a different value for version byte 2.
Data Sheet
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2000-05
C504
Absolute Maximum Ratings Parameter Storage temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation Symbol min. Limit Values max. 150 6.5 C V V mA mA - - - - - - 65 - 0.5 - 0.5 - 10 - Unit Notes
TST VDD VIN
- -
VDD + 0.5
10 |100 mA|
PDISS
-
1
W
-
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C504 SAF-C504 SAK-C504 Analog reference voltage Analog ground voltage Analog input voltage CPU clock
Data Sheet
Symbol min.
Limit Values max. 5.5 0 0 - 40 - 40 4 70 85 125 4.25
Unit V V C
Notes - - -
VDD VSS TA TA TA VAREF VAGND VAIN fCPU
VSS - 0.1 VAGND
1.75
44
VDD + 0.1 VSS + 0.2 VAREF
20
V V V
- - -
MHz -
2000-05
C504
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C504 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C504 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C504. DC Characteristics (Operating Conditions apply) Parameter Input low voltage (except EA, RESET, CTRAP) Input low voltage (EA) Input low voltage (RESET, CTRAP) Symbol Limit Values min. max. 0.2 VDD - 0.1 0.2 VDD - 0.3 V V - - Unit Test Condition
VIL VIL1
SR - 0.5 SR - 0.5
VIL2
SR - 0.5
0.2 VDD + V 0.1
-
Input high voltage (except XTAL1, RESET and VIH CTRAP) Input high voltage to XTAL1 VIH1 Input high voltage to RESET and CTRAP Output low voltage (Ports 1, 2, 3, COUT3) Output low voltage (Port 0, ALE, PSEN) Output high voltage (Ports 1, 2, 3)
SR 0.2 VDD + 0.9 SR 0.7 VDD
VDD + 0.5 V VDD + 0.5 V VDD + 0.5 V
0.45 0.45 - - - V V V
11)
- -
VIH2 SR 0.6 VDD VOL
CC -
IOL = 1.6 mA1) IOL = 3.2 mA1) IOH = - 80 A IOH = - 10 A IOH = - 800 A
VOL1 CC - VOH CC 2.4
0.9 VDD
Output high voltage (Ports 1, 3 pins in push-pull VOH1 CC 0.9 VDD mode and COUT3)
V
Data Sheet
45
2000-05
C504
DC Characteristics (cont'd) (Operating Conditions apply) Parameter Output high voltage (Port 0 in external bus mode, ALE, PSEN) Logic 0 input current (Ports 1, 2, 3) Logical 1-to-0 transition current (Ports 1, 2, 3) Input leakage current (Port 0, EA) Pin capacitance Overload current Programming voltage (C504-2E) Power Supply Current Parameter Active mode C504-2R 24 MHz 40 MHz C504-2E 24 MHz 40 MHz Idle mode C504-2R 24 MHz 40 MHz C504-2E 24 MHz 40 MHz Power-down C504-2R mode C504-2E At EA/VPP
in prog. mode
Symbol
Limit Values min. max. - - - 50 - 650 1 10 5 12.1
Unit Test Condition
VOH2 CC 2.4
0.9 VDD
V
IOH = - 800 A2) IOH = - 80 A2) VIN = 0.45 V VIN = 2 V
0.45 < VIN < VDD
IIL ITL ILI CIO IOV VPP
SR - 10 SR - 65 CC - CC - SR - SR 10.9
A A A pF mA
fc = 1 MHz, TA = 25 C
7) 8)
V
11.5 V 5%10)
Symbol
Limit Values typ.8) 27.4 43.1 20.9 31.0 14.6 22.4 12.3 16.1 1 35 - max.9) 35.9 57.2 27.9 41.5 19.3 31.3 16.1 20.9 30 60 30
Unit Test Condition mA mA mA mA mA mA mA mA A A mA -
5) 4)
C504-2E
IDD IDD IDD IDD IDD IDD IDD IDD IPD IPD IDDP
VDD = 2 ... 5.5 V 3)
Data Sheet
46
2000-05
C504
Notes: 1) Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VDD; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS; VAGND = VSS; all other pins are disconnected. 4) IDD (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; EA = Port 0 = Port 1 = RESET = VDD; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port 0 = VDD; all other pins are disconnected; 6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VDD and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 7) Not 100 % tested, guaranteed by design characterization. 8) The typical IDD values are periodically measured at TA = + 25 C and VDD = 5 V but not 100% tested. 9) The maximum IDD values are measured under worst case conditions (TA = 0 C or - 40 C and VDD = 5.5 V) 10)This VPP specification is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must be programmed with VPP = 12 V 5%. 11)For the C504-2E ES-AA-step the VIH min. for EA is 0.8 VDD.
Data Sheet
47
2000-05
C504
60 mA
MCD03367
DD 50
40
DD max DD typ
C504-2R
Active Mode
Active Mode Idle Mode 30 Idle Mode 20 10 0 0 5 10 15 20 25 30 35 MHz 40 f OSC
60 mA
MCD03368
DD 50
40
DD max DD typ
C504-2E
Active Mode Active Mode
30 Idle Mode 20 10 0 0 5 10 15 20 25 30 35 MHz 40 f OSC Idle Mode
Figure 23
IDD Diagram
Data Sheet
48
2000-05
C504
Power Supply Current Calculation Formulas Parameter Active mode C504-2R Symbol Formula
IDD typ 0.98 x fOSC + 3.9 IDD max 1.33 x fOSC + 4.0 IDD typ 0.63 x fOSC + 5.75 C504-2E IDD max 0.85 x fOSC + 7.5 IDD typ 0.51 x fOSC + 2.35 Idle mode C504-2R IDD max 0.75 x fOSC + 1.3 IDD typ 0.24 x fOSC + 6.5 C504-2E IDD max 0.30 x fOSC + 8.86 Note: fosc is the oscillator frequency in MHz. IDD values are given in mA.
A/D Converter Characteristics (Operating Conditions apply) Parameter Analog input voltage Sample time Symbol Limit Values min. max.
1)
Unit Test Condition
VAIN SR tS CC
Conversion cycle time
tADCC CC
VAGND VAREF V - 64 x tIN ns 32 x tIN 16 x tIN 8 x tIN - 384 x tIN ns 192 x tIN 96 x tIN 48 x tIN
- - 2 4
Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 42) Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 43)
Total unadjusted error
TUE
CC
LSB VSS + 0.5 V VIN VDD - 0.5 V4) LSB VSS < VIN < VSS + 0.5 V VDD - 0.5 V < VIN < VDD4)
Internal resistance of reference voltage source Internal resistance of analog source
RAREF SR
-
tADC/250 k
- 0.25
tADC in [ns] 5) 6)
RASRC SR
- -
tS/500
- 0.25 50
k pF
tS in [ns] 2) 6)
6)
ADC input capacitance CAIN CC Notes see next page.
Data Sheet
49
2000-05
C504
Clock Calculation Table Clock Prescaler Ratio / 32 / 16 /8 /4 ADCL1, 0 1 1 0 0 1 0 1 0
tADC
32 x tIN 16 x tIN 8 x tIN 4 x tIN
tS
64 x tIN 32 x tIN 16 x tIN 8 x tIN
tADCC
384 x tIN 192 x tIN 96 x tIN 48 x tIN
Further timing conditions:
Notes:
tADC min = 500 ns tIN = 2/fOSC = 2 tCLCL
1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time, the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion, the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.
Data Sheet
50
2000-05
C504
AC Characteristics for C504-L / C504-2R / C504-2E (Operating Conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 12-MHz clock Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz max. Unit
min. max. min. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN
Notes:
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX
CC CC CC SR CC CC SR SR
127 43 30 - 58 215 - 0 - 75 - 0
- - - 233 - - 150 - 63 - 302 -
2tCLCL - 40 -
ns ns ns ns ns ns ns ns ns
tCLCL - 40 tCLCL - 23
-
- - -
4tCLCL - 100 ns
tCLCL - 25
- 0 -
3tCLCL - 35 - -
3tCLCL - 100 ns
tPXIZ1) SR tPXAV1) CC tAVIV SR tAZPL CC
tCLCL - 20
- -
tCLCL - 8
- 0
5tCLCL - 115 ns
1) Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers.
Data Sheet
51
2000-05
C504
AC Characteristics for C504-L / C504-2R / C504-2E (cont'd) Parameter Symbol 12-MHz clock Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz max. Unit
min. max. min. External Data Memory Characteristics
tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD Address valid to WR or RD tAVWL WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD
RD pulse width
CC 400 - CC 400 - CC 114 - SR - SR 0 SR - SR - SR - 252 - 97 517 585
6tCLCL - 100 6tCLCL - 100 2tCLCL - 53 - 0 - - - 3tCLCL - 50 4tCLCL - 130
- - - 5tCLCL - 165 - 2tCLCL - 70 8tCLCL - 150 9tCLCL - 165 3tCLCL + 50 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CC 200 300 CC 203 - CC 43 CC 33 CC 33 CC - 123 - - 0
tCLCL - 40 tCLCL - 50
7tCLCL - 150
tCLCL + 40
- - - 0
CC 433 -
tCLCL - 50
-
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 12 MHz min. Oscillator period High time Low time Rise time Fall time
Data Sheet
Unit
max. 294 ns ns ns ns ns
2000-05
tCLCL tCHCX tCLCX tCLCH tCHCL
SR SR SR SR SR
83.3 20 20 - -
52
tCLCL - tCLCX tCLCL - tCHCX
20 20
C504
AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (Operating Conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 24-MHz clock min. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN
Notes: 1) Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers.
Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz max.
Unit
max. min.
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX
CC 43 CC 17 CC 17 SR - CC 22 CC 95 SR - SR 0
- - - 80 - - 60 - 32 - 148 -
2tCLCL - 40
- - - - - -
ns ns ns ns ns ns ns ns ns
tCLCL - 25 tCLCL - 25
-
4tCLCL - 87 ns
tCLCL - 20
3tCLCL - 30 - 0 -
3tCLCL - 65 ns
tPXIZ1) SR - tPXAV1) CC 37 tAVIV SR - tAZPL CC 0
tCLCL - 10
- -
tCLCL - 5
- 0
5tCLCL - 60 ns
Data Sheet
53
2000-05
C504
AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (cont'd) Parameter Symbol 24-MHz clock Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz max. Unit
min. max. min. External Data Memory Characteristics
tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD tAVWL Address valid to WR WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD
RD pulse width External Clock Drive Parameter
CC 180 CC 180 CC 56 SR - SR 0 SR - SR - SR - CC 75 CC 67 CC 17 CC 5 CC 170 CC 15 CC -
- - - 118 - 63 200 220 175 - 67 - - - 0
6tCLCL - 70 6tCLCL - 70 2tCLCL - 27 - 0 - - - 3tCLCL - 50 4tCLCL - 97
- - - 5tCLCL - 90 - 2tCLCL - 20 8tCLCL - 133 9tCLCL - 155 3tCLCL + 50 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCLCL - 25 tCLCL - 37
7tCLCL - 122
tCLCL + 25
- - - 0
tCLCL - 27
-
Symbol
Limit Values Variable Clock Freq. = 3.5 MHz to 24 MHz min. max. 294
Unit
Oscillator period High time Low time Rise time Fall time
Data Sheet
tCLCL tCHCX tCLCX tCLCH tCHCL
SR 41.7 SR 12 SR 12 SR - SR -
54
ns ns ns ns ns
2000-05
tCLCL - tCLCX tCLCL - tCHCX
12 12
C504
AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (Operating Conditions apply)1) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol 40-MHz clock min. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN
Notes: 1) SAK-C504 is not specified for 40 MHz operation. 2) Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers.
Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz max.
Unit
max. min.
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX
CC 35 CC 10 CC 10 SR - CC 10 CC 60 SR - SR 0
- - - 55 - - 25 - 20 - 65 -
2tCLCL - 15 -
ns ns ns ns ns ns ns ns ns
tCLCL - 15 - tCLCL - 15 -
-
4tCLCL - 45 ns
tCLCL - 15 -
3tCLCL - 15 - - 0 - -
3tCLCL - 50 ns
tPXIZ2) SR - tPXAV2) CC 20 tAVIV SR - tAZPL CC - 5
tCLCL - 5
- -
tCLCL - 5
- -5
5tCLCL - 60 ns
Data Sheet
55
2000-05
C504
AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (cont'd) Parameter Symbol 40-MHz clock Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz max. Unit
min. max. min. External Data Memory Characteristics
tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD tAVWL Address valid to WR WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD
RD pulse width External Clock Drive Parameter
CC 120 - CC 120 - CC 35 SR - SR 0 SR - SR - SR - CC 60 CC 70 CC 10 CC 5 CC 5 CC - 38 150 150 90 - 40 - - 0 - 75
6tCLCL - 30 6tCLCL - 30 2tCLCL - 15 - 0 - - - 3tCLCL - 15 4tCLCL - 30
- - - 5tCLCL - 50 - 2tCLCL - 12 8tCLCL - 50 9tCLCL - 75 3tCLCL + 15 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCLCL - 15 tCLCL - 20
7tCLCL - 50
tCLCL + 15
- - - 0
CC 125 -
tCLCL - 20
-
Symbol
Limit Values Variable Clock Freq. = 3.5 MHz to 40 MHz min. max. 294
Unit
Oscillator period High time Low time Rise time Fall time
Data Sheet
tCLCL tCHCX tCLCX tCLCH tCHCL
SR 25 SR 10 SR 10 SR - SR -
56
ns ns ns ns ns
2000-05
tCLCL - tCLCX tCLCL - tCHCX
10 10
C504
t LHLL
ALE
t AVLL t LLPL t LLIV t PLIV
PSEN
t PLPH
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 24
Program Memory Read Cycle
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 25
Data Sheet
Data Memory Read Cycle
57 2000-05
C504
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 26
Data Memory Write Cycle
t CLCL VDD- 0.5V
0.7 VDD 0.2 VDD - 0.1
0.45V
t CHCL
t CLCX t CLCH
t CHCX
MCT00033
Figure 27
External Clock Cycle
Data Sheet
58
2000-05
C504
AC Characteristics of Programming Mode (VDD = 5 V 10%; VPP = 11.5 V 5 %; TA = 25 C 10 C)
Parameter
Symbol
Limit Values min. max. - - - - - - - - - - 75 20 - 20 - - 285.7 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 83.3
Unit ns ns ns ns ns ns ns ns s ns ns ns ns ns s ns ns
tPAW tPMS PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD tPAS
PALE pulse width falling edge Address hold after PALE, PROG, or PRD tPAH falling edge
tPCS Address, data hold after PROG or PRD tPCH tPMS PMSEL setup to PROG or PRD tPMH PMSEL hold after PROG or PRD tPWW PROG pulse width tPRW PRD pulse width tPAD Address to valid data out tPRD PRD to valid data out tPDH Data hold after PRD tPDF Data float after PRD tPWH1 PROG high between two consecutive
Address, data setup to PROG or PRD PROG low pulses PRD high between two consecutive PRD tPWH2 low pulses XTAL clock period
Note:
tCLKP
VPP = 11.5 V 5% is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must
be programmed with VPP = 12 V 5%.
Data Sheet
59
2000-05
C504
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
Port 0
D0-D7
PROG
t PWH t PCS t PWW t PCH
MCT03369
Note: PRD must be high during a programming read cycle
Figure 28
Programming Code Byte - Write Cycle Timing
Data Sheet
60
2000-05
C504
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
t PAD
Port 0 D0-D7
t PDH
t PRD
PRD
t PDF t PWH
t PCS
t PRW
t PCH
MCT03370
Note: PROG must be high during a programming read cycle
Figure 29
Verify Code Byte - Read Cycle Timing
Data Sheet
61
2000-05
C504
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCS t PMS
PROG
t PCH t PMH t PDH t PWW t PMS t PRD t PRW t PMH t PDF
PRD Note : PALE should be low during a lock bit read / write cycle
MCT03371
Figure 30
Lock Bit Access Timing
PMSEL1,0
L, H
Port 2
e. g. FD H
t PCH
Port 0 D0-7
t PCS t PRD t PMS
PRD
t PDH t PDF t PMH
t PRW
MCT03372
Note : PROG must be high during a programming read cycle
Figure 31
Version Byte Read Timing
Data Sheet
62
2000-05
C504
ROM/OTP Verification Characteristics for C504-2R / C504-2E ROM Verification Mode 1 (C504-2R only) Parameter Address to valid data Symbol min. Limit Values max. 10 tCLCL ns Unit
tAVQV
-
P1.0 - P1.7 P2.0 - P2.5
Address
t AVQV
Port 0 Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.5 = A8 - A13 Data: P0.0 - P0.7 = D0 - D7 Data OUT Inputs: P2.6, P2.7, PSEN = V SS ALE, EA = V IH RESET = V IH2
MCT03428
Figure 32
ROM Verification Mode 1
Data Sheet
63
2000-05
C504
ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. - - 4 tCLCL - - 6 ns ns ns ns ns MHz - - - 8 tCLCL - 4 Unit
tAWD tACY tDVA tDSA tAS
1/tCLCL
tCLCL
-
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 33
ROM Verification Mode 2
Data Sheet
64
2000-05
C504
V DD -0.5 V
0.2 VDD +0.9 Test Points 0.2 VDD -0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VDD - 0.5 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and VILmax for a logic `0'.
Figure 34
AC Testing: Input, Output Waveforms
VLoad +0.1 V VLoad VLoad -0.1 V
Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA
Figure 35
AC Testing: Float Waveforms
Figure 36
Recommended Oscillator Circuits for Crystal Oscillator
Data Sheet
65
2000-05
C504
Package Information P-MQFP-44 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 66
Dimensions in mm 2000-05
GPM05622
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